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19-0479; Rev 1; 7/97
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
________________General Description
The MAX3664 low-power transimpedance preamplifier for 622Mbps SDH/SONET applications consumes only 85mW. Operating from a single +3.3V supply, it converts a small photodiode current to a measurable differential voltage. A DC cancellation circuit provides a true differential output swing over a wide range of input current levels, thus reducing pulse-width distortion. The differential outputs are back-terminated with 60 per side. The transimpedance gain is nominally 6k. For input signal levels beyond approximately 100Ap-p, the amplifier will limit the output swing to 900mV. The MAX3664's low 55nA input noise provides a typical sensitivity of -33.2dBm in 1300nm, 622Mbps receivers. The MAX3664 is designed to be used in conjunction with the MAX3675 clock recovery and data retiming IC with limiting amplifier. Together, they form a complete 3.3V, 622Mbps SDH/SONET receiver. In die form, the MAX3664 is designed to fit on a header with a PIN diode. It includes a filter connection, which provides positive bias for the photodiode through a 1k resistor to VCC. The device is also available in 8-pin SO and MAX packages.
KIT ATION EVALU BLE AVAILA
____________________________Features
o Single +3.3V Supply Operation o 55nARMS Input-Referred Noise o 6k Gain o 85mW Power o 300A Peak Input Current o 200ps Max Pulse-Width Distortion o Differential Output Drives 100 Load o 590MHz Bandwidth
MAX3664
_______________Ordering Information
PART MAX3664E/D MAX3664ESA MAX3664EUA* TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE Dice 8 SO 8 MAX
* Contact factory for package availability.
________________________Applications
SDH/SONET Receivers PIN/Preamplifier Receivers Regenerators for SDH/SONET
Pin Configuration appears at end of data sheet.
__________________________________________________Typical Application Circuit
VCC (+3.3V) 0.01F VCC (+3.3V) 1k 100pF (FILT) INREF2 INREF1 VCC OUT+ 100 LIMITING AMP 47nF DATA AND CLOCK RECOVERY DATA 47nF
MAX3664
IN GND
OUTCOMP
CLK
MAX3675
400pF ( ) ARE FOR MAX3664E/D (DICE) ONLY.
________________________________________________________________ Maxim Integrated Products
1
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622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET MAX3664
ABSOLUTE MAXIMUM RATINGS
VCC ........................................................................-0.5V to +5.5V Continuous Current IN, INREF1, INREF2, COMP, FILT....................................5mA OUT+, OUT-...................................................................25mA Continuous Power Dissipation (TA = +85C) SO (derate 5.88mW/C above +85C) ........................383mW MAX (derate 4.1mW/C above +85C) .....................268mW Operating Junction Temperature (die) ..............-40C to +150C Processing Temperature (die) .........................................+400C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V 0.3V, COMP = GND, 100 load between OUT+ and OUT-, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted.) (Notes 1, 2) PARAMETER Input Bias Voltage Gain Nonlinearity Supply Current Small-Signal Transimpedance Output Common-Mode Level Power-Supply Rejection Ratio Differential Output Offset Output Impedance (per side) Maximum Output Voltage Filter Resistor (die only) PSRR VOUT ZOUT VOUT(max) RFILT IIN = 300A 800 1000 f < 1MHz, referred to output IIN = 200A, CCOMP = 400pF 40 20 7 60 75 950 1200 ICC z21 SYMBOL VIN CONDITIONS IIN = 0 to 300A IIN = 0 to 20A IIN = 0 Differential output 12 4.5 25 6 VCC - 1.3 MIN TYP 0.8 MAX 0.95 5 35 7.5 UNITS V % mA k V dB mV mV
Note 1: Dice are tested at Tj = +27C. Note 2: MAX package tested at TA = +25C to +85C.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V 0.3V, CCOMP = 400pF, CIN = 1.1pF, outputs terminated into 50, 8-pin SO package in MAX3664 EV board, TA = +25C, unless otherwise noted.) (Notes 3, 4) PARAMETER Small-Signal Bandwidth Low-Frequency Cutoff Pulse-Width Distortion (Note 5) 2A to 100A peak input current, 50% duty cycle, 1-0 pattern PWD 100A to 300A peak input current, 50% duty cycle, 1-0 pattern in CIN = 0.3pF (Note 6), IIN = 0 CIN = 1.1pF (Note 6), IIN = 0 80 55 73 86 200 nA 6 SYMBOL BW-3dB CONDITIONS Relative to gain at 10MHz MIN TYP 590 150 100 ps MAX UNITS MHz kHz
RMS Noise Referred to Input
Note 3: AC Characteristics are guaranteed by design. Note 4: CIN is the total capacitance at IN. Note 5: PWD = 2 x Pulse width - Period | | 2 Note 6: DC to 470MHz, measured with 3-pole Bessel filter at output. 2 _______________________________________________________________________________________
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
__________________________________________Typical Operating Characteristics
(VCC = +3.3V, CCOMP = 400pF, TA = +25C, unless otherwise noted.)
MAX3664
INPUT-REFERRED NOISE vs. TEMPERATURE
MAX3664-01
SMALL-SIGNAL GAIN vs. FREQUENCY
MAX3664-02
PULSE-WIDTH DISTORTION vs. TEMPERATURE
MAX3664 IN EV BOARD 150
MAX3664-03
100 90 80 70 NOISE (nA) 60 50 40 30 20 10 0 -40 -5 30 65 CIN IS SOURCE CAPACITANCE PRESENTED TO DIE. INCLUDES PACKAGE PARASITIC, PIN DIODE, AND PARASITIC INTERCONNECT CAPACITANCE 470MHz BANDWIDTH CIN = 1.5pF
80 78 76 74 GAIN (dB) 72 70 68 66 64 62 60 COMP CONNECTED THROUGH 400pF TO GROUND COMP CONNECTED TO GROUND MAX3664 IN EV BOARD
200
IIN = 300A PWD (ps) 100
CIN = 1.0pF CIN = 0.5pF
50 IIN = 100A 0
-50 10k 100k 1M 10M 100M 1G 10G -40 -25 0 25 45 65 85 FREQUENCY (Hz) AMBIENT TEMPERATURE (C)
100
JUNCTION TEMPERATURE (C)
INPUT-REFERRED RMS NOISE CURRENT vs. DC INPUT CURRENT
MAX3664-04
SMALL-SIGNAL TRANSIMPEDANCE vs. TEMPERATURE
MAX3664-05
BANDWIDTH vs. TEMPERATURE
CIN = 0.5pF 600 BANDWIDTH (MHz) CIN = 1.0pF 550 CIN = 1.5pF 500 CIN IS SOURCE CAPACITANCE PRESENTED TO DIE. INCLUDES PACKAGE PARASITIC, PIN DIODE, AND PARASITIC INTERCONNECT CAPACITANCE -40 -5 30 65 100
MAX3664-06
1000 CSTC = 0.5pF 470MHz BANDWIDTH RMS NOISE CURRENT (nA)
6400 VCC = 3.6V 6300 TRANSIMPEDANCE () 6200 6100 6000 5900 MEASUREMENT FREQUENCY = 20MHz VCC = 3V
650
100
450
10 0.1 1 10 100 1000 DC INPUT CURRENT (A)
5800 -40 -5 30 65 100 JUNCTION TEMPERATURE (C)
400 JUNCTION TEMPERATURE (C)
LOW-FREQUENCY CUTOFF vs. AVERAGE INPUT CURRENT
MAX3664-07
DATA-DEPENDENT JITTER vs. INPUT SIGNAL AMPLITUDE
EXTINCTION RATIO > 10 100 CCOMP = 100pF CCOMP = 200pF CCOMP = 400pF CCOMP = 800pF 40 20 0 INPUT: 213 - 1 PRBS CONTAINS 72 ZEROS 0 50 100 150 200 250 300 PEAK-TO-PEAK JITTER (ps)
MAX3664-08
OUTPUT COMMON-MODE VOLTAGE (REFERENCED TO VCC) vs. TEMPERATURE
MAX3664-09
300 LOW-FREQUENCY CUTOFF (kHz) 250 200 150 100 50 0 0 20 40 60 80 CCOMP = 200pF CCOMP = 400pF CCOMP = 1000pF CCOMP = 50pF CCOMP = 100pF
120
-1.15 -1.20 VCC = 3.0V
80 60
COMMON-MODE VOLTAGE (V)
-1.25
-1.30
VCC = 3.3V
-1.35
VCC = 3.6V
-1.40 -40 -20 0 20 40 60 80 100 PEAK-TO-PEAK AMPLITUDE (A) AMBIENT TEMPERATURE (C)
100 120 140 160
AVERAGE INPUT CURRENT (A)
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622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET MAX3664
_____________________________Typical Operating Characteristics (continued)
(VCC = +3.3V, CCOMP = 400pF, TA = +25C, unless otherwise noted.)
OUTPUT AMPLITUDE vs. TEMPERATURE
INPUT = 300Ap-p 700 AMPLITUDE (mV) 600 500 400 300 200 -40 -20 0 20 40 60 80 100 300ps/div 300ps/div AMBIENT TEMPERATURE (C) INPUT: 213 - 1 PRBS CONTAINS 72 ZEROS VCC = 3.3V VCC = 3.0V 10mV/ div 100mV/ div VCC = 3.6V
MAX3664-10
EYE DIAGRAM (INPUT = 10Ap-p)
MAX3664-11
EYE DIAGRAM (INPUT = 300Ap-p)
MAX3664-12
800
INPUT: 213 - 1 PRBS CONTAINS 72 ZEROS
_____________________Pin Description
VCC
PIN
NAME VCC IN INREF1, INREF2 GND OUT+
FUNCTION +3.3V Supply Voltage
D1 RF
1k
(FILT)
1
2 3, 4 5 6
Signal Input Input References 1 and 2. Connect to photodetector AC ground. Ground Noninverting Voltage Output. Current flowing into IN causes VOUT+ to increase. Inverting Voltage Output. Current flowing into IN causes VOUT- to decrease. External Compensation Capacitor for DC cancellation loop. Connect 400pF or more from COMP to GND for normal operation. Connect COMP directly to GND to disable the DC cancellation loop. Filter Connection. Provides positive bias for photodiode through a 1k resistor to VCC. See Step 3: Designing Filters. (This pad is accessible on the die only.)
IN INREF1 Q3 TRANSIMPEDANCE AMP R3 R4 Q4 INREF2 DC CANCELLATION AMP R2 OUTQ1 PARAPHASE AMP 6k VCC VCC Q2 R1 OUT+
VCC
7
OUT-
8
COMP
MAX3664
COMP ( ) ARE FOR MAX3664E/D (DIE) ONLY.
--
FILT*
* MAX3664E/D (die) only. Figure 1. Functional Diagram
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622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
________________Detailed Description
The MAX3664 is a transimpedance amplifier designed for 622Mbps SDH/SONET applications. It comprises a transimpedance amplifier, a paraphase amplifier with emitter-follower outputs, and a DC cancellation loop. Figure 1 is a functional diagram of the MAX3664. component, this is not a problem. Preamplifier noise will increase for signals with significant DC component.
MAX3664
___________Applications Information
The MAX3664 is a low-noise, wide-bandwidth transimpedance amplifier that is ideal for 622Mbps SDH/ SONET receivers. Its features allow easy design into a fiber optic module, in four simple steps.
Transimpedance Amplifier
The signal current at IN flows into the summing node of a high-gain amplifier. Shunt feedback through RF converts this current to a voltage with a gain of 6k. Diode D1 clamps the output voltage for large input currents. INREF1 is a direct connection to the emitter of the input transistor, and must be connected directly to the photodetector AC ground return for best performance.
Step 1: Selecting a Preamplifier for a 622Mbps Receiver
Fiber optic systems place requirements on the bandwidth, gain, and noise of the transimpedance preamplifier. The MAX3664 optimizes these characteristics for SDH/SONET receiver applications that operate at 622Mbps. In general, the bandwidth of a fiber optic preamplifier should be 0.6 to 1 times the data rate. Therefore, in a 622Mbps system, the bandwidth should be between 375MHz and 622MHz. Lower bandwidth causes pattern-dependent jitter and a lower signal-to-noise ratio, while higher bandwidth increases thermal noise. The MAX3664 typical bandwidth is 590MHz, making it ideal for 622Mbps applications. The preamplifier's transimpedance must be high enough to ensure that expected input signals generate output levels exceeding the sensitivity of the limiting amplifier (quantizer) in the following stage. The MAX3675 clock recovery and limiting amplifier IC has an input sensitivity of 3.6mVp-p, which means that 3.6mVp-p is the minimum signal amplitude required to produce a fully limited output. Therefore, when used with the MAX3664, which has a 6k transimpedance, the minimum detectable photodetector current is 600nA. It is common to relate peak-to-peak input signals to average optical power. The relationship between optical input power and output current for a photodetector is called the responsivity (), with units Amperes/Watt (A/W). The photodetector peak-to-peak current is related to the peak-to-peak optical power as follows: Ip-p = (Pp-p)() Based on the assumption that SDH/SONET signals maintain a 50% duty cycle, the following equations relate peak-to-peak optical power to average optical power and extinction ratio (Figure 2): Average Optical Power = PAVE = (P0 + P1) / 2 Extinction Ratio = re = P1 / P0 Peak-to-Peak Signal Amplitude = Pp-p = P1 - P0 Therefore, PAVE = Pp-p (1 / 2)[(re + 1) / (re - 1)]
5
Paraphase Amplifier
The paraphase amplifier converts single-ended inputs to differential outputs, and introduces a voltage gain of 2. This signal drives a pair of internally biased emitter followers, Q2 and Q3, which form the output stage. Resistors R1 and R2 provide back-termination at the output, absorbing reflections between the MAX3664 and its load. The output emitter followers are designed to drive a 100 differential load between OUT+ and OUT-. They can also drive higher output impedances, resulting in increased gain and output voltage swing.
DC Cancellation Loop
The DC cancellation loop removes the DC component of the input signal by using low-frequency feedback. This feature centers the signal within the MAX3664's dynamic range, reducing pulse-width distortion on large input signals. The output of the paraphase amplifier is sensed through resistors R3 and R4 and then filtered, amplified, and fed back to the base of transistor Q4. The transistor draws the DC component of the input signal away from the transimpedance amplifier's summing node. The COMP pin sets the DC cancellation loop's response. Connect 400pF or more between COMP and GND for normal operation. Connect the pin directly to GND to disable the loop. The DC cancellation loop can sink up to 300A of current at the input. When operated with CCOMP = 400pF, the loop takes approximately 20s to stabilize. The MAX3664 minimizes pulse-width distortion for data sequences that exhibit a 50% duty cycle. A duty cycle other than 50% causes the device to generate pulsewidth distortion. DC cancellation current is drawn from the input and adds noise. For low-level signals with little or no DC
_______________________________________________________________________________________
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
In a system where the photodiode responsivity is 0.9A/W and the extinction ratio is 10, the MAX3664/ MAX3675 receiver with 670nA gain sensitivity will deliver a fully limited output for signals of average optical power larger than: (600nA / 0.9A/W)(1 / 2)(11 / 9) = 407nW -33.9dBm Sensitivity is a key specification of the receiver module. The ITU/Bellcore specifications for SDH/SONET receivers require a link sensitivity of -27dBm with a bit error rate (BER) of 1E - 10. There is an additional 1dB power penalty to accommodate various system losses; therefore, the sensitivity of a 622Mbps receiver must be better than -28dBm. Although several parameters affect sensitivity (such as the quantizer sensitivity and preamplifier gain, as previously discussed), most fiber optic receivers are designed so that noise is the dominant factor. Noise from the highgain transimpedance amplifier, in particular, determines the sensitivity. The noise generated by the MAX3664 can be modeled with a Gaussian distribution. In this case, a BER of 1E - 10 corresponds to a peak-to-peak signal amplitude to RMS noise ratio (SNR) of 12.7. The MAX3664's typical input-referred noise, in, (bandwidthlimited to 470MHz) is 55nARMS. Therefore, the minimum input for a BER of 1E - 10 is (12.7 x 55nA) = 700nAp-p. Rearranging the previous equations in these terms results in the following relation: Optical Sensitivity (dBm) = -10log[(in / )(SNR)(1/2)(re + 1) / (re - 1)(1000)]
MAX3664
At room temperature, with re = 10, SNR = 12.7, in = 55nA, and = 0.9A/W, the MAX3664 sensitivity is -33.2dBm. At +85C, noise increases to 62nA and sensitivity decreases to -32.7dBm. The MAX3664 provides 4.7dB margin over the SDH/SONET specifications, even at +85C. The largest allowable input to an optical receiver is called the input overload. The MAX3664's largest input current (Imax) is 300Ap-p, with 200ps of pulse-width distortion. The pulse-width distortion and input current are closely related (see Typical Operating Characteristics). If the clock recovery circuit can accept more pulse-width distortion, a higher input current might be acceptable. For worst-case responsivity and extinction ratio, = 1A/W and re = , the input overload is: Overload (dBm) = -10log (Imax)(1 / 2)(1000) For Imax = 300A, the MAX3664 overload is -8.2dBm.
Step 2: Selecting Time Constants
A receiver built with the MAX3664 will have a bandpass frequency response. The low-frequency cutoff causes unwanted data-dependent jitter and sensitivity loss. Because SDH/SONET data streams contain scrambled data, certain data sequences may generate continuous successions of 1s or 0s. The low-frequency cutoff forces the output of such sequences to zero, ultimately causing a sensitivity reduction. The SDH specifications state that a receiver must be able to handle up to 72 consecutive bits of the same value within the data. Therefore, choose the low-frequency cutoff to ensure an acceptable amount of data-dependent jitter and sensitivity loss. Determine the reduction in signal-to-noise ratio due to a transitionless sequence of duration t as follows: SNRloss = 1 - e-t / = 1-e-(2fct) where is the time constant of the offset correction, fc is the low-frequency cutoff, and t is the time for 72 bits (116ns for a 622Mbps data rate). Suppose that the receiver should not have more than 0.25dB (6%) of sensitivity loss due to a 72-bit transitionless sequence. This means that: (1 - e-(2fc)(116ns)) < 0.06 fc = (ln 0.94) / [(-2)(116ns)] = 85kHz (max) The loss of sensitivity is a concern only when the SNR is small (close to 12.7), which occurs with input currents less than 3Ap-p.
POWER
P1
PAVE
P0
TIME
Figure 2. Optical Power Definitions
6 _______________________________________________________________________________________
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
The cutoff frequency also affects the data-dependent jitter (DDJ). DDJ due to low-frequency cutoff can be approximated as droop / slope, where the slope in V/sec is measured at the 50% crossing of an eye diagram, and droop is the loss-of-signal to noise calculated above as 1 - e-(2fct). The slope at the 50% crossing is typically two times the 10% to 90% slope, which is approximately 0.35 / bandwidth. For a 622Mbps receiver with a 470MHz bandwidth, the 10% to 90% rise time is approximately 750ps. The slope through the 50% crossing will be approximately: Amplitude (2)(0.8) / 750ps = 1.6 Amplitude / 750ps = 2E9 Amplitude V/sec DDJ = 2 [Amplitude (1 - e-(2fct))] / [ 2.0E9 Amplitude ] = (1 - e-(2fct)) / (1E9) OR fc = -ln[1 - (1.0E9)(DDJ)] / [2t] If the maximum allowable DDJ is 100ps, and t = 112ns for a 72-bit sequence, then the maximum low-frequency cutoff is 150kHz. Several circuits in the receiver can determine the lowfrequency cutoff. In a receiver using the MAX3664 and MAX3675, there are three locations for concern: 1) The MAX3664's DC cancellation circuit. 2) The coupling capacitors between the MAX3664 outputs and MAX3675 inputs. 3) The MAX3675's offset correction circuit. The highest cutoff frequency in the system determines the amount of data-dependent jitter created. The time constants of the MAX3675's offset correction and of the coupling capacitors should be separated by a factor of ten (one decade) to prevent low-frequency oscillations. For example, select the offset correction of the MAX3664 to set the receiver cutoff frequency. Note that the MAX3664's low-frequency cutoff increases with average input current. Since DDJ increases with fc, it follows that DDJ increases as average input increases. When the input signal is large enough to limit the outputs, however, DDJ does not increase. Therefore, the maximum DDJ results from the lowest input that causes the MAX3664 to have limited outputs (see Typical Operating Characteristics), which is about 150Ap-p. When selecting a capacitor for the COMP pin that achieves your desired DDJ, use the data from Typical Operating Characteristics at IINPUT = 150A. In summary, use the following method to select the lowfrequency cutoff that will provide the sensitivity and DDJ required for SDH/SONET receivers: 1) Determine the longest time without transitions. 2) Determine the acceptable loss of SNR ratio, and the acceptable DDJ due to the transitionless time. 3) Estimate the low-frequency cutoff required for either the worst-case SNR loss or for DDJ. 4) Select the location in the receiver to determine the highest cutoff frequency. Normally, the MAX3664 would determine the dominant low-frequency cutoff. Then select all other low-frequency cutoffs one decade lower. 5) Select a capacitor for the COMP pin from the Typical Operating Characteristics graphs. 400pF is adequate for most 622Mbps SDH/SONET applications.
MAX3664
_______________________________________________________________________________________
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622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET MAX3664
Step 3: Designing Filters
The MAX3664's noise performance is a strong function of the circuit's bandwidth, which changes over temperature and varies from lot to lot. The receiver sensitivity can be improved by adding filters to limit this bandwidth. Filter designs can range from a one-pole filter using a single capacitor, to more complex filters using inductors. Figure 3 illustrates two examples: the simple filter provides moderate roll-off with minimal components, while the complex filter provides a sharper rolloff and better transient response. Supply voltage noise at the cathode of the photodiode produces a current I = CPHOTO (V/t), which reduces the receiver sensitivity. C PHOTO is the photodiode capacitance. The FILT resistor of the MAX3664, combined with an external capacitor (see Typical Operating Circuit) can be used to reduce this noise. The external capacitor (C FILT ) is placed in parallel with the photodiode. Current generated by supply noise is divided between CFILT and CPHOTO. The input noise current due to supply noise is (assuming the filter capacitor is much larger than the photodiode capacitance): INOISE =
a)
SIMPLE, 1-POLE, 530MHz FILTER
MAX3664
60 60 C1 5pF
RL 100
b)
3-POLE, 470MHz BESSEL FILTER
MAX3664
60 1.2pF 60
15.5nF
7.3pF
RL 100
15.5nF
(VNOISE )(CPHOTO ) (RFILT )(CFILTER )
Figure 3. Filter Design Examples
If the amount of tolerable noise is known, then the filter capacitor can be easily selected: CFILT =
(VNOISE )(CPHOTO ) (RFILT )(INOISE )
For example, with maximum noise voltage = 100mVp-p, CPHOTO = 0.5pF, RFILT = 1k, and INOISE selected to be 5nA (1/10 of MAX3664 input-referred noise): CFILT = 0.1 0.5E - 12 / 1000 5E - 9 = 10nF
( )(
) [(
)(
)]
Step 4: Designing a Low-Capacitance Input
Noise performance and bandwidth are adversely affected by stray capacitance on the input node. Select a low-capacitance photodiode and use good high-frequency design and layout techniques to minimize capacitance on this pin. The MAX3664 is optimized for 0.5pF of capacitance on the input-- approximately the capacitance of a photodetector diode sharing a common header with the MAX3664 in die form.
Photodiode capacitance changes significantly with bias voltage. With a 3.3V supply voltage, the reverse voltage on the PIN diode is only 2.5V. If a higher voltage supply is available, apply it to the diode to significantly reduce capacitance. Take great care to reduce input capacitance. With the SO and MAX versions of the MAX3664, the package capacitance is about 0.3pF, and the PC board between the MAX3664 input and the photodiode can add parasitic capacitance. Keep the input line short, and remove power and ground planes beneath it. Packaging the MAX3664 into a header with the photodiode provides the best possible performance. It reduces parasitic capacitance to a minimum, resulting in the lowest noise and the best bandwidth.
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_______________________________________________________________________________________
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
INREF1 and INREF2
Connect INREF1 and INREF2 as close to the AC ground of the photodetector diode as possible. The photodetector AC ground is usually the ground of the filter capacitor from the photodetector anode. The total loop (from INREF1/INREF2, through the bypass capacitor and the diode, and back to IN) should be no more than 2 cm. long.
VCC
MAX3664
Wire Bonding
For high current density and reliable operation, the MAX3664 uses gold metallization. Make connections to the die with gold wire only, and use ball bonding techniques (wedge bonding is not recommended). Die-pad size is 4 mils square, with a 6 mil pitch. Die thickness is 12 mils.
FILTER CAP OUT+ PIN DIODE OUT-
IN
VCC and Ground
Use good high-frequency design and layout techniques. The use of a multilayer circuit board with separate ground and VCC planes is recommended. Take care to bypass VCC and to connect the GND pin to the ground plane with the shortest possible traces.
OUT+ OUT-
COMP
Figure 4. Suggested Layout for TO-46 Header
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9
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET MAX3664
___________________Pin Configuration
TOP VIEW
___________________Chip Topography
OUTOUT+
COMP
GND
VCC 1 IN 2 INREF1 3 INREF2 4
8
COMP OUTOUT+ GND
V CC
0.032" (0.81mm)
MAX3664
7 6 5
INREF2
SO/MAX
IN FILT 0.037" (0.94mm) INREF1
TRANSISTOR COUNT: 73 SUBSTRATE CONNECTED TO GND
10
______________________________________________________________________________________
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET
________________________________________________________Package Information
8LUMAXD.EPS
MAX3664
______________________________________________________________________________________
11
622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET MAX3664
___________________________________________Package Information (continued)
SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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